1. Field of the Invention
The present invention relates to a method of controlling a semiconductor storage circuit, more particularly to a method of controlling a continuous write and read operation to be implemented in a pipeline circuit.
2. Description of the Prior Art
Recently, with the advance of the operation speed of a CPU, there has been an increasing demand for a semiconductor storage device which operates at high speed.
However, because of a physical limit against the minute fractionization of the device manufacturing process or an increased chip size due to desired enlargement of the capacity, it can not be said that the demand for the high speed semiconductor storage device has been sufficiently satisfied.
Therefore, as a means for solving the above problem, there is proposed DRAM which has an internal pipeline structure.
FIG. 1 is a circuit diagram in a block form showing a conventional DRAM which has a pipeline structure. In the block diagram, a data-in latch 40 comprises a write buffer 41 which receives write data from a terminal DO, a D-F/F circuit 42 for latching an output of the write buffer 41 with the timing of an internal clock signal ICLK1, a D-F/F circuit 43 for latching an output of the D-F/F circuit 42 with the timing of an internal clock signal ICLK2, and a write amplifier 44 for receiving an output of the D-F/F circuit 43 and outputting it to a R/W bus 80. A buffer 61 outputs data on the R/W bus 80 to a sense amplifier 60, and a buffer 62 receives an output of the sense amplifier 60 to output it to the R/W bus 80. A plurality of pairs of bit lines between the sense amplifier 60 and a memory cell array 70 constitutes a write/read path. The memory cell array 70 includes a plurality of memory cells disposed in the directions of rows and columns in a form of array. A data-out latch 50 comprises a buffer 51 which receives data on the R/W bus 80, a D-F/F circuit 52 for latching an output of the buffer 51 with the timing of an internal clock signal ICLK3, and a data-out buffer 53 for receiving an output of the D-F/F circuit 52 and transmitting the received output to the terminal DO as read data. A column address latch 10 comprises column address buffers 11 which receive address signals A0, A1, A2, ---, An from the outside, respectively, and a D-F/F circuit 12 for latching an output of the column address buffer 11 with the timing of the internal clock signal ICLK1. A burst counter 120 generates column addresses based on column addresses latched in the D-F/F circuit 12. The number of column addresses to be generated equals to the burst length. A column decoder 20 is supplied with outputs of the burst counter 12. A column address latch 30 comprises inverter IV1 and IV2 and an N channel type transistor Trl which receives the internal clock signal ICLK2 on its gate, and receives an output from the column decoder 20 to output a column switch signal. Row address buffers 90 receive address signals A0, A1, A2, . . . , An from the outside, respectively. A row decoder 100 receives and decodes the outputs of row address buffers 90 and drives word lines 110 connected with the memory cell 70.
Write operation of DRAM shown in FIG. 1 will next be described also with reference to FIG. 2.
In FIG. 2, when, in a cycle C1, a combination of data supplied to input terminals is selected as an active command at the leading edge of the external clock signal CLK from the outside, then the data on address terminals at that time are latched in the row address buffers 90 as row addresses and are decoded to select a word line.
Next, in a cycle C3, when a combination of data supplied to input terminals is Selected as a write command, the data A1 on the address terminal at that time is latched in the D-F/F12 with the timing of the internal clock signal ICLK1 as a column address. When the write command is inputted, the internal clock signals ICLK1, ICLK2, and ICLK3 are generated by an internal clock generation circuit which is not shown. The internal clock signal ICLK1 becomes a high level only one time in the cycle C3 in which the write command is inputted. The internal clock signal ICLK2 becomes a high level in a cycle C4 and C5 delayed from the write command by one cycle and two cycles, respectively. The internal clock signal ICLK3 becomes a high level only one time in the cycle C5 delayed from the write command by two cycles. When the internal clock signal ICLK1 becomes a high level state only one time in the cycle C3, the address data A1 is transmitted to the column decoder 20 to be latched therein.
Next, when the internal clock signal ICLK2 becomes a high level only one time in the cycle C4, the address data A1 is transmitted to the column address latch 30 and latched therein during the time period of the high level state. On the other hand, data DIN inputted from the terminal DO as write data in the cycle C3 is transmitted by the internal clock signals ICLK1 and ICLK2 of the high level state and is written to the sense amplifier 60 through the R/W bus 80 in the cycle C4. Thereafter, the data DIN is written in the memory cell from the sense amplifier 60 in a cycle C5.
The internal clock signal ICLK2 resets the address data latched in the column address latch 30 in the cycle C5. Also a precharge command for resetting a row address can first be inputted in the cycle C5 in which data is written into the memory cell.
Read operation of DRAM shown in FIG. 1 will next be described with reference to FIG. 3.
When a read command is inputted in a cycle C3, data A2 on the address terminal at this time is latched in the column address buffer 10 as a column address in the same manner as in the write time, and internal clock signals ICLK1, ICLK2, ICLK3 are generated in the same way as in the write operation. When the internal clock signal ICLK1 becomes a high level only one time in the cycle C3, the address data A2 is transmitted to the column decoder 20 and latched therein.
Subsequently, when the internal clock signal ICLK2 becomes a high level in a cycle C4, the column address latch 30 is selected to transmit the address data A2 to the column address latch 30 during this cycle and then the address data A2 is latched in the column address latch 30. When the column address latch is selected, the data in the sense amplifier 60 is transmitted through the R/W bus 80 and latched by the data-out latch 50 in the cycle C4.
Following which, when the internal clock signal ICLK3 becomes a high level in the cycle C5, the data latched in the data-out latch 50 is outputted to the terminal DO.
In the read operation, the data stored in the sense amplifier 60 is read in the cycle C4, and hence it becomes possible to input a precharge command in the cycle C4.
The operations shown in FIG. 2 and FIG. 3 are operations with the burst length being equal to 1, and in which only one address is accessed for one write command or one read command and also the data is inputted or outputted only once for the command. The burst length is determined by the mode register set operation before the active command is inputted.
FIG. 4 shows the write operation in the case of burst 10 length being equal to 4. When a write command is inputted in the cycle C3 and address data A1-1 is inputted, then address data A1-2, A1-3, A1-4 are produced in the cycles C4, C5, C6, respectively, by means of the internal burst counter 120. At this time, the internal clock signals ICLK1, ICLK2, ICLK3 are energized 4, 5, 6 and times, respectively, and 4-bit data is written thereby. Since 1-bit data is written in one cycle during the burst operation, when the burst length is 4, writing of 4-bit data is completed in six cycles which starts from the cycle for inputting the write command.
With this conventional method of controlling the semiconductor storage circuit, three clock cycles are required from the input of the write command to data writing in a memory cell and three clock cycles are also required from the input of the read command to data reading from the memory cell. Therefore, if write, and read operations are each operated for 1 bit on the same word line, at least six clock cycles are needed, yielding poor efficiency of a pipeline circuit.